.. title: kingst-la2016
.. slug: kingst-la2016
.. date: 2023-10-01 01:14:43 UTC+02:00
.. tags: logic-analyzer, python, reverse-engineering
.. category: 
.. link: 
.. description: tools to work with Kingst LA2016 logic analyzer
.. type: text

today i revisited a hobby-project: reverse engineering the Kingst LA2016
USB logic analyzer.
its a 16 channel, 200 MSa/S USB2 device.
i did the actual protocol reverse engineering in february/march 2020, mostly throwing
together python notebooks and looking at linux usbmon traces.
later in 2020 i did actually provide a `patch for libsigrok <https://github.com/sigrokproject/libsigrok/pull/60>`_ which was
merged and seems to work at least on linux. but that is a C project and
for me not a lot of fun to work on that code (they have a strict coding
style which is just too far from my own). i did also create a
firmware-extraction tool to get the MCU-firmware and fpga-bitstream from
the original vendor binaries. (because they can probably not be
re-distributed directly).

i revisited it as i currently again have some need for a logic analyzer
that i can automate. but i wanted to avoid all that libsigrok "overhead"
and decided to make a "clean" re-implementation in pure-python (but using
pyusb / libusb).
that way it is easier to use on "cooperate linux machines".

so here it is after 5h of toying. simple stuff works, i did not look at
corner-cases and i also did not invest any time on the "continuous
downloading & sampling" mode.

https://gitlab.com/fastflo/kingst_la

the other idea was to use this as an example project for me to do it in rust.